Bipolar random access memories (RAMs) are formed in a matrix of a plurality of rows and columns each containing a plurality of memory cells. Each cell in each column is coupled to a pair of bit lines and each cell in each row is connected to a pair of word lines. Selection of a particular cell in the matrix is accomplished by applying a voltage or current to the particular row and column that is common to the desired cell.
The plurality of memory cells in each row are enabled, or placed in a selected state, by the application of a voltage to the top word line in that row so that current may flow through the cell from the lower word line. The lower word line is generally connected through a suitable current source to a voltage reference, such as circuit ground, which operates to control or limit the current through the row of cells. Unfortunately, a row containing a plurality of cells is highly capacitive so that when a row is deselected by removal of the top word line voltage, the top word line will remain at its high voltage selected state until the row capacitance has been discharged. The time required for such capacitive discharge will obviously slow the operation of the memory.
The circuitry to be described and claimed herein senses the deselection of a word line to turn on a transistor switch to a large current dump source which very rapidly discharges all cell capacitance. The circuitry prevents large D.C. currents from flowing through any of the RAM rows and the high dump current cannot flow through the cells when the top word line is switched from its low deselected level to the selected or high state.